Intel Mask Data Synthesis Engineer in Boise, Idaho
Process Engineers design and plan the layout for such processes as hardening, washing, laminating, etching, engraving, polishing, painting, plating, and other material processing operations. Plans sequence of operations and specifies procedures for cutting, shaping, and otherwise preparing basic material, exercising judgment in compromising between conflicting requirements, economic evaluation of methods, and operator effectiveness and comfort. Conducts tests and measurements throughout stages of production to determine control over such variables as temperature, density, specific gravity, pressure, and viscosity. Establishes and submits processing requirements to be met in designing and acquiring processing equipment. Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement.
Thorough knowledge of Calibre, Hercules in Unix/Linux environments.
Detailed knowledge of DFII, K2VIEW and other Industry standard CD capture/measurement tools.
In-depth Knowledge of scripting languages like (Perl & Python preferred.)
Comprehensive knowledge of Tape-out and Mask Generation Flows for High volume manufacturing.
Knowledge of Fab areas like Lithography/ OPC/ Scribe/Metal Fill and CMP.
Good understanding of GDS2/SF/OASIS format & layout hierarchy and layer maps.
Ability to handle multiple complex projects/tape-outs at the same time and deliver results in a timely and orderly manner with minimal errors.
Good verbal & written communication skills with Excel, Visio & Power Point proficiency.
MS in EE, Physics, Computer Science, Material Science or Chemistry.
At least 5 years relevant semiconductor industry experience in mask synthesis in a high volume manufacturing setting.
Description The Intel NVM (Non Volatile Memory) Process Technology Development group is responsible for developing state of the art NVM memory technologies like 3D-NAND & 3D-Xpoint. As a mask synthesis engineer within this organization you will be chartered with coding and maintaining mask algorithms, DRC run sets and will be involved in prep work on the mask data prior to tape-out of reticles for current and future NVM technologies.
Responsibilities include, but are not limited to: • Coding and maintaining of mask synthesis algorithms and DRC run sets for modification and validation of GDS2/OASIS data to specification of technology development engineers (DR team) which will be developed based on constant process/reticle/layout interaction requirements. • Write clear concise code in Calibre and Hercules languages without errors. • Document and present code in Generator/Tape out Code Design Reviews. • Write and maintain Calibre based run sets for design rule check’s (DRC) for various formats of layout and reticle data (GDS2/Stream files/ Oasis). • Write pattern matching checks in Calibre for complicated layouts which are required for High Volume manufacturing. • Write metal fill code and optimize algorithms to pass density and DFM flows. • Interface with multiple groups like Process Integration, Design Rules, CAD, Layout, Scribe and Mask shops with patience and thoroughness. • Drive projects across multi-disciplinary teams focusing on layout and mask generation issues. • Drive diagnostic projects across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask synthesized data.
US, California, Santa Clara;
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