Intel IP Functional Safety Engineer (Transceiver IP) in San Jose, California

Job Description

Intel Programmable Solutions Group (PSG) is focusing on development of Field Programmable Gate Array (FPGA) and associated IP products for the Advance Driving (ADAS) market. As such these products need to comply with Functional Safety requirements. The IP Functional Safety Engineer will be responsible for executing the Functional Safety process to ensure that PSG IP meets the requirements.

Duties will include, but not limited to:

  • Executing safety analysis (Failure Mode Effect and Diagnostic Analysis, Fault Tree Analysis) on PSG IP products. Specifically for Transceiver IP, which controls the transceiver in Intel FPGAs

  • Identifying and characterizing mitigation measures for preventing or detecting faults potentially affecting integrated circuits

  • Executing fault injection testing to verify the performance of such mitigation measures

  • Preparing and maintaining of specific documents and data like functional specifications, safety analysis reports, and safety verification plans

  • These duties will require excellent verbal and written communication, collaboration skills, and cross-functional leadership

Please be informed that Intel is proactively trying to find candidates for a position and that may, or may not, be available for all location(s) at this time. If you're interested in this position, we would encourage you to apply, and our hiring team will be glad to contact you if/when relevant.


  • Knowledge of functional safety basics, related standards such as IEC 61508 and ISO 26262, Failure Modes, Effects and Diagnostics Analysis (FMEDA) and Fault Tree Analysis (FTA) processes

  • BSEE, or related

  • 4 years of experience in SoC/IP or MSEE/related with 2 years of experience in SoC/IP Design

  • Experience in HDL such as Verilog, VHDL and SystemVerilog

Additional (Preferred) Qualifications

  • FPGA Experience

  • Experience in functional verification of digital circuit and/or front to back digital design flow

  • Knowledge of requirement management tools like IBM DOORS Next Generation

  • Working knowledge in any scripting language (e.g. Python)

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.