Intel MIPI IP Design Engineer in San Jose, California

Job Description

Minimum Requirements: -BS in Electrical Engineering, or related. -At least 5 years of experience in FPGA or ASIC IP architecture, Design, Integration, and verification -3 years of experience in MIPI Camera Serial Interface CSIPreferred Requirements -MSEE, MSCS, or MS in Computer Engineering or related -Proficient with scripting Languages like Gmake/Perl/Tcl/Python. -Experience with tools such as VCS, NCSIM, Verdi, and Spyglass -Experience with Lint, CDC, Synthesis, equivalence checking. -Experience with Multiple Clock Domains and Asynchronous Interfaces. -Familiarity with automated front end design flows

Qualifications

As an IP front end design engineer in the IP development department, you will be developing & maintaining critical hardware IP used in latest FPGAs. You will work in a dynamic team dealing with multiple complex hardware IP. Your responsibilities will include, but not limited to architecture, design, integration, and verification of hardware IP.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

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