Intel I/O Circuit Intern in Santa Clara, California
Responsibilities may be quite diverse of an exempt technical nature. U.S.
Responsibilities may be quite diverse of an exempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Possible work includes:
Transistor level circuit design.
Timing analysis and partition.
Architecture tradeoff study.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
The ideal candidate should exhibit the following behavioral traits:
• Strong Communication and teamwork skills.
• Candidate must be pursuing a Master's or PhD Degree in Electrical Engineering, or any other related field.
• Six months experience or equivalent coursework in the following fields:
Analog circuit fundamentals.
High-speed serial link theory and operation.
• Familiarity with high-level modeling language.
• Knowledge of PCIe or other serial I/O industry standards.
Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
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