Intel IP/SoC Senior Physical Design Technical Lead in Santa Clara, California
Technical Leadership for the design, integration and convergence from RTL to GDS of complex IP/subsystems/SoCs.
Provides the guidance & mentoring for large teams and drives horizontal methodologies to benefit multiple IP/Subsystem teams in design robustness and productivity.
Oversees definition, design, verification, and documentation for IP/SoC development.
Engages with architecture design, logic design, and system simulation.
Defines module interfaces/formats for simulation.
Performs Physical design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Floor-planning, Timing and electrical robustness convergence for IPs and SoCs.
Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Must have Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science with 12+ years of experience, or a Master's degree in Electrical Engineering, Computer Engineering or Computer Science with 10+ years of experience
Experience should include SoC /IP design development over many projects
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
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