Intel SoC DFx Engineer in Santa Clara, California

Job Description

Job Description: SoC DFx Engineer - Santa Clara, CAThe Scalable Performance CPU Development Group SDG is searching for an energetic and passionate DFx engineer to part of a team passionate about DFx in our SOCs to deliver high quality products.We are looking for someone who has passion around improving the way we solve complex problems through the work of the team as wells as their own direct contributions. Working experiences include digging in deep on technical challenges, empowering a team to succeed, and working in collaboration with design, DV, physical world and system teams. You also understand that relationships formed with other peers, teams, and organizations is key to success in SoC, package and system level test.Direct Responsibilities:Works on design, verification, and documentation for SoC, MCP package, and system level test development. Performs Logic design for Dfx components into functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Performs all aspects of the SoC design for test flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. Interact and drive vendor relationships to support development.The ideal candidate will be able to demonstrate the following behaviors:Ability to work effectively with both internal and external teams & customers is expected.Ability to mentor other engineers and technically guide them.Experience with silicon which include processor cores and custom logic working together.Strong problem solving/leadership skillsStrong written and verbal communication skillsFacilitator of direct and open communication, diversity of opinion, and debate.


Minimum Requirements:BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 8+ years of relevant experience in SOC/system design/verification or MS degree with 6+ years or PHD with 4+ years of directly related experience with SOC/Package/Board debug and test.Candidates must have the following:Proven expertise in debug and test of Silicon based products. Extensive experience with designing/dealing with manufacturing test requirements.The ability work as an individual and as part of a team to deliver a product which is debug and test friendly starting from the creation of the spec, design, verification, and finally to productization.Expertise in dealing and designing with complex IP's from different sources onto the same piece of silicon understanding debug and test requirements.Understand system and package implications of the silicon design decisions.Preferred Skills:Experience design for test and debug, at Silicon, Multichip package and Board levelExperience with board design/debug and challenges

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