Intel Senior Circuit Design Engineer in Austin, Texas

Job Description

The CPU Circuit Technology team is looking for a highly motivated and technically savvy experienced individual to join our team as Digital Circuit Design Engineer.

Our team is responsible for developing full-custom as well as compiler based Large Signal Arrays custom multi-ported register file, ROMs, SRAMs, power delivery and standard cell characterization for Atom CPU Hard IP and its derivatives.

This will be a fast-paced dynamic environment where you will work in the high performance, low power CPU design group on a wide spectrum of circuit activities ranging from technical readiness, device and/or cell characterization, bit-cell simulations, critical path simulations and design custom blocks to meet stringent Power/Performance/Area constraints. You will be involved in methodology definition tasks as well as executing to project schedules.

Behavioral traits for this position would include logical thinking, very good verbal/written communication, excellent interpersonal skills, ability to prioritize work, multi-tasking, good analytical and problem solving skills.


Minimum Requirements:

  • Master's degree in Electrical Engineering and/or Computer Engineering with 4+ years of experience in a high-tech company OR a Bachelor's degree in Electrical Engineering and/or Computer Engineering with 6 years of experience in a high-tech company.

  • Hands-on expertise and strong fundamentals in the following areas:

  • Very Large Scale Integration VLSI

  • Complementary MOS CMOS circuits design

  • Digital logic and optimizations.Low power implementation techniques

  • CKT design trade-off for power, performance and area

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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