Intel SOC Emulation Verification Engineer in Austin, Texas

Job Description

Come join the Scalable CPU performance Development Group SDG in Austin as a Emulation based SOC verification Engineer. In this role you will be working directly with other emulation prototyping teams, designers, Validation engineers, Firmware and system engineers to validate next generation server processors through emulation based modeling and prototyping for future Intel SoCs.

The Xeon Server CPU validation team enables future generations of CPUs that power Cloud, Enterprise, and Data Center! Functional validation teams are organized around technologies which include Integrated IO PCIE, UPI, and Virtualization, Memory, Reset, Fuses, Power Management, RAS, Security, Cache coherency and Mesh.

We are looking for sharp collaborative engineers who pay extra attention to engineering details, passionate about top quality validation, and interested in engineering/validation of complex leading edge projects. They will create and execute validation plans, and debug critical failures allowing for high quality products delivered to customers like Google, Amazon, Facebook, and more. Must be comfortable working in a team setting and interfacing with architecture, design, and other validation teams. They will proactively engage with IP/validation collateral providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution


Minimum Qualifications: -

  • Must have a Bachelor's degree or Master's degree in Electrical Engineering, Computer Engineering with relevant experience of at least 3 years-

  • Strong Computer architecture knowledge-

  • Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog based verification techniques.-

  • Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments.- Experience in SW Programming/scripting and debug such as C, C++, Perl, Python

Preferred Qualifications -

  • Experience with x86 ISA and/or Experience in developing assembly tests - Experience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce or FPGA prototyping systems.-

  • Experience in building emulation based models for large scale designs-

  • Familiarity with OVM/UVM

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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