Intel Big Core Backend Integration - Section Layout Owne in Folsom, California

Job Description

This is an entry level position and will be paid accordingly.

The job opening is for a Section Integration Owner with the DDG Big Core CPU team in Folsom. The primary responsibility is to individually own multiple Core sections from forecasting area and routing requirements all the way through delivering tape-in quality section that meets stringent timing, PV, RV and verification constraints using the most updated physical design and verification tools along with process advancements and improvements designed for high volume manufacturability. This is accomplished by working through all phases of chip design starting from custom polygon editing, floor planning, routing, IO assembly, packaging, and verification.

Your responsibilities will include but not be limited to:

  • Accurately forecast section requirements backed by area analysis, routing constraint studies and timing

  • Independently plan, track and solve complex process and design rule requirements

  • Manage multiple physical design constraints, assemble, route and converge the section to meet forecasted schedule

  • Independently plan and break down tasks into manageable, intermediate milestones given project constraints

  • Proactively communicate and collaborate with the circuit design, timing owners and layout teams

  • Consistently provide timely feedback and relevant data throughout the project cycle for all Functional Unit Blocks (FUBs) including datapath, static arrays, ROM, RLS design and special HIPs/SIPs

  • Develop creative solutions towards improving self and team productivity by writing simple scripts

The ideal candidate should exhibit the following behavioral traits:

  • Strong engineering, problem solving and analytical skills

  • Strong verbal and written communication skills

  • Ability to work well in a highly dynamic, cross-geography collaborative environment


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must have a BS or MS degree in Electrical Engineering (EE), Computer Engineering (CE), or other engineering/applied sciences degree. At BS level, this U.S. position is open to U.S. Workers Only. A U.S. Worker is someone who is either a U.S. Citizen, U.S. National, U.S. Lawful Permanent Resident, or a person granted Refugee or Asylum status by the U.S. Government. Intel will not sponsor a foreign national for this position.

At least 6 months of experience in:

  • Physical design methodologies and sub-micron technology

  • Place&route, physical verification (DRC/LVS/Antenna)

  • Electronic circuit functionality and behaviors (passive and active circuit structures)

  • Complementary Metal-Oxide Semiconductor (CMOS) and Very Large Scale Integration (VLSI) component design principles

Preferred Qualifications:

  • Experience in writing and producing software code using languages such as PERL and TCL

  • Knowledge in Unix/Linux operating systems

  • Knowledge of CAD physical design software

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Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....