Intel Big Core Logic Design Engineer in Folsom, California

Job Description

Intel's BigCore IP team located in Folsom, within IACG organization is looking for senior logic designers to work on some of the clusters Instruction Fetch & Decode, Out of Order execution that make up the IA Core. Candidate will be working on logic/RTL design responsibilities for some of the units within each cluster, interfacing with various stake holders backend, validation, architects, etc to deliver high quality Intel Core IP to Client/Server SoC teams. Some of the other responsibilities include good coordination with stake holders including cross-site, participation in various TR activities, debug functional issues, provide logic support for backend convergence issues, etc.


Candidate must possess the below minimum qualifications to be considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor.

Minimum Qualifications:

  • Must have a BS or MS in Electrical Engineering or Computer Engineering

  • Minimum of 6 years for BS and 4 year for MS of experience in logic design

  • Good understanding of Computer Architecture/Micro-Architecture concepts Logic design experience in RTL modeling, integration

  • Strong debug analytical skills Experience with System Verilog and/or VCS Simulator, Perl, C/C+Preferred Qualifications:

  • Good understanding of X86 Core micro-architectural concepts preferred

  • Familiarity with validation concepts

Inside this Business Group

The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.

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