Intel DFX/DFT Design Engineers in Folsom, California

Job Description

Are you passionate about computer graphics and disrupting the industry with your innovation? Working with leading Engineers on Intel's latest GPU/CPU architecture? Do you love collaborating with a diverse teams to help achieve Best–In-Class visual experiences that enable users to immerse themselves in a new visual future? Then our Visual Technologies Team VTT has opportunities for you. The Hardware team is within VTT and we design and validate the future Processor Graphics engines for mobile, desktop and server platforms that will lead the graphics market in power and performance.

We are looking for DFX/DFT Design Engineers to join our team and who is ready to make significant impact in the graphics and visual computing. As a member of the VTT Graphics Hardware DFx group, you will be responsible for the following activities:

  • You will work on the design, RTL/GLS validation, automation, and/or timing analysis in one of the following DFx domains: Controller, Scan, Array DFT, Functional DFT, or DFD.

  • You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for.

Behavioral traits that we are looking for:

  • Strong written and verbal communication skills

  • Strong leadership in driving execution across different functional team

  • Possess strong teamwork, problem-solving and influencing skills along with abilities to work with different geographical locations

What we offer you:

  • We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.

  • As the 7th largest global company in innovation and new technology, we foster a collaborative, supportive and boredom-free environment, where the brightest minds in the world come together to achieve exceptional results.

  • We offer a competitive salary and financial benefits such as bonuses, opportunities to buy Intel stock at a discounted rate, or Intel stock awards (eligibility at the discretion of Intel Corp.).

  • We provide unique benefits that cater to your needs: flexible work hours, private medical plan, travel medical care, life and disability insurance.

  • We encourage working hard, but also playing hard! Intel employees are eligible for creative perks such as special recreation activities, discounts on various products and services, and much more.


Minimum Skills and Experience that we are looking for:

BS Degree in Electrical Engineering, Computer Engineering, or other related field with 4+ years of experience. A Masters with 3 years of experience is preferred.

Your experience should be in the following prioritized areas:

  • Good understanding of at least one of the key DFx features such as Controller, Scan, Array DFT, Functional DFT, or DFD.

  • Good familiarity/knowledge in the following ASIC design and/or validation areas:

  • Scripting language e.g. Perl

  • Verilog and/or System Verilog

  • RTL/GLS simulation/environment using industry standard simulator e.g. VCS/modelsim

  • Structural Design flows including timing, routing, placement, or clocking analysis.

Preferred Skills and Experience that will make you stand out:

  • Post-silicon enabling/debug experience of DFx features on tester or system validation platforms is preferred

Are you passionate about this opportunity and ready to help us create the next generation of technologies that will transform the future for decades to come? Then we encourage you to apply and be part of our team.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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