Intel High Speed I-O Design Engineer in Folsom, California
Within the I/O design team of Nonvolatile Solutions Group, the candidate will be responsible for developing circuits for nonvolatile memory components. More specifically, you will be focusing on developing DDR4/DDR5 receiver circuits utilizing 3DXP memory process technologies. You will be responsible for implementing and validating receiver equalization circuits such as CTLE and DFE, driving the physical design implementation and leading post silicon activities for these designs.
Minimum of 5 years of circuit design experience using CMOS technologies.
Minimum of 3 Years of experience with multi GT/s interfaces such as PCIe, QPI, DDR, etc.
Minimum of 3 Years of experience in multi GT/s receiver designs with equalization techniques
Minimum of 5 years of hands-on experience in circuit design, using validation tools and methodologies including but not limited to Cadence, Hspice, starRC, Monte Carlo, Aging, etc.
Additional Required Skills:
- Demonstrated leadership in time management and problem solving skills:
Experience in circuit modeling in VerilogA. Understanding of signal integrity of I/O channels
Experience in the design of PLL, DLL, high speed clock distribution and power delivery
Inside this Business Group
Non-Volatile Solutions Memory Group: The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices. The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.
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