Intel IP Logic Design Engineer in Folsom, California
Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.
This position is in PCH circuit front-end development where you will be working closely within a team of RTL design/validation engineers, micro-architects, and architects on PCH circuit IP targeting a wide range of client and server PCH products. The development environment is dynamic and fast-moving, focused on high-quality results, frequently entailing multiple projects under concurrent development. You will be encouraged to take informed risks, to continuously seek useful design innovations and process improvements, and to have fun while doing so.
Responsibilities include but are not limited to:
Analysis, interpretation, and assessment of hardware architectural specifications defining feature requirements for PCH circuit IP.
Contributing towards development of logic designs and RTL coding for PCH circuit IP. Design implementations must meet functional and performance requirements, physical/structural design constraints (timing, area, power), as well as design for security, design for manufacturing and other quality criteria.
Running through RTL design verification flows: model build, lintra, spyglass-lp, spyglass-dft, Nebulon, CDC and emulation.
Characterization and analysis of performance and power results; implementation of corresponding design modifications and optimizations as required to achieve power and performance targets.
Execution of synthesis flows in FEBE and guide physical design convergence.
Strong communication, interpersonal, and problem-solving skills
Motivation, self-direction, and ability to work effectively both independently and as part of a diverse cross-geographic team
You must possess these minimum qualifications to be initially considered for this position.
- Bachelor's or Master's Degree in Electrical and/or Computer Engineering
At least 2+ years of work experience with the following:
Computer architecture/digital IC design
Logic design implementation and verification using hardware description language (RTL) and verification languages such as Verilog or System Verilog; applying good coding style
Usage/execution of logic simulation, synthesis and familiarity with logic development flows
- Prior experience or training in clocking design, IO design and familiar with low power design technique is a plus for consideration of this position.
Inside this Business Group
US, California, Santa Clara
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....