Intel Mask Designer in Folsom, California
Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job.
Roles and Responsibilities
� Performs as a highly proficient technical individual contributor or specialist on complex layout and leadership assignments
� Leadership responsibilities could include large-scale block layout, complex layout blocks, small to medium scope section lead, small to medium scope layout projects with some mentoring or guidance, development or improvement projects, tool evaluations, etc.
� Can coordinate, facilitate and monitor the daily activities of a small to large group of support resources within their section or project team
� While holding a leadership role is able to contribute to the layout execution at a prominent level
� With minimal supervision, prioritizes workload to successfully manage multiple tasks and responsibilities concurrently
� With minimal supervision, manages daily operations within their assignments, showing appropriate consideration for established project objectives and standard project methodologies
� With minimal supervision drives high level layout execution on moderately complex blocks.
� Given established boundary conditions and constraints, develops detailed task lists, forecasts resource requirements, and creates long range schedules for sections and small projects
� Frequently involved in developing the skills of less experienced layout designers through formal training, coaching or mentoring
� Proactively addresses and communicates issues impacting productivity and works to resolve those roadblocks
� 2 year technical degree in VLSI or Physical Design/Mask Design
� Highly proficient with industry based (CAD) layout tools including: Cadence (Virtuoso, VXL),
Strong background in verification (Calibre DRC, LVS and others)
� Knowledge and experience in block/chip level layout and pitch (wordline, bitline) block layout
� Experience with tight pitch, highly sensitive layouts (mirrored/stepped), wordline and bitline decoder layout using various metal stacks, dual/quad pitch socket interfaces (2D/3D), 6T or 8T bitcell SRAM layout, high/low voltage layout integration
� Strong engineering problem solving and analytical skills
� Knowledge of CMOS and (VLSI) component design principles and experience with 3D architecture
� Experience of basic electronic circuit functionality and behaviors (passive and active circuit structures)
� Layout section/FUB lead experience
� Adept at developing process limited designs and pathfinding activities for future process nodes
� Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)
� Experience in building memory arrays from the ground up
� Experience with layout of the standard cells for APR, custom standard cell library, scribe layouts, and runset regression test cases
� Ability to accomplish the activities with high quality, minimal supervision, and on time delivery
� Ability to work with engineers on scheduling, execution, and verifying complex designs
� Strong verbal and written communication skills
� Ability to work well in a team environment
� Experienced with UNIX, as well as MS Windows and web based tools
Inside this Business Group
Non-Volatile Solutions Memory Group: The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices. The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....