Intel Post Silicon Functional Debug Engineer in Folsom, California

Job Description

The Core SRT charter is to debug Core related logical failures, provide Ucode patch solutions for the failures, and add new capabilities to improve the debug process. SRT engineers are leading engineers who are experts in Core architecture and micro-architecture, debug tools and CPU debug features.

The work is done by a specially selected team which allows its members a personal and professional development in many challenging fields. The engineer will be part of the team and involved in all its activities such as debug and root cause of functional issues, debug scripts development, definition of DFD features and development of Ucode patches.

The job requires excellent analysis skills, creativity, innovative thinking and ability to collaborate with other design, validation and debug teams across various Intel sites. If you have the relevant experience, high motivation and desire to be part of an exclusive team dealing with high-end technology, we will be delighted to hear from you.

Qualifications

Must have requirements:

B.Sc. Or Master's Degree in Computer Engineering, Electrical Engineering or Software Engineering.

4+ years of experience in the industry.

Preferred requirements:

Familiarity with CPU architecture or micro-architecture .

Knowledge in Assembly.

Experience in Post Silicon environment .

Experience in Verification .

Experience in Linux environment.

Prior experience working at Intel.

Inside this Business Group

The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.

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