Intel Pre-Silicon Validation Engineer in Folsom, California

Job Description

In this role you will create Pre-Silicon functional validation tests to verify that the systems meet design requirements. Creates test plans for register-transfer level (RTL) validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.

Job responsibilities include writing verification test plans, and then writing tests to execute those plans. Development of verification collateral such as behavioral checkers, coverage monitors, test generators or score-boards is often required to enable test plan execution. To be successful at this role you will need to debug failing tests, then work with designers and architects to resolve bugs. Successful verification engineers can anticipate failure modes, and write punishing test content to stress the design and identify bugs. You will also analyze coverage gaps and devise strategies to fill coverage holes. The quality of the design and the final product is directly proportional to the quality of the design verification work. Other responsibilities include working with RTL and Architect teams to define verification strategy, planning and execution, driving verification methodologies etc.

Behavioral traits for this position include:

  • Strong problem solving

  • Tolerance of ambiguity.

Qualifications

Minimum Qualifications

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science or other science/engineering related field.

  • At least 3 years' experience designing or validating SoCs, CPUs, PCHes, or IP blocks required

  • Min 2 years’ experience with software/programming languages i.e. C++, Java, Visual Basic, .NET, Perl, Python, etc.

  • Detailed knowledge of RTL language such as System Verilog/Verilog.

Additional Profile Characteristics Preferred

  • Proven skill with coverage driven validation

  • Knowledge with computer architecture and micro-architecture.

  • Experience in IP/SOC ASIC Validation.

  • Experience in OVM/UVM, VCS Simulator and Unified Power Format (UPF)

  • Expertise with software design and coding.

  • Familiarity with x86 core architecture and instruction set

Inside this Business Group

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....