Intel Principal Engineer- DDR PHY Architect Lead in Folsom, California
Candidate will lead the PHY Architecture development for modular, scalable, high-performance, low-power, next-generation Memory Interfaces on latest Intel process technologies for multiple exciting Intel SoC products.
Defines, Documents and Designs PHY Architectures for High-Performance/Low-Power Memory Interfaces supporting multiple Intel SoC applications. Determines creative design approaches and parameters. Determines, specifies and evaluates the viability of complex hardware features and structures and ensures that firmware and hardware designs interface correctly. Designs framework for particular functions. Defines, documents and tests processes for inclusion into technical platforms, subsystem specifications, input/output and working parameters for hardware and/or firmware compatibility. Identifies, analyzes and resolves subsystem and/or SoC design weaknesses. Influences the shaping of future products by significantly contributing to the architecture used across design families. Provides multilayered technical expertise for next generation initiatives.
Key Responsibilities include but not limited to:
Innovate and own System Modeling, Architecture, Design and Development of high performance, low power IO PHY meeting latest Memory Industry Standards for LPDDR, DDR Or Proprietary On-Package Interconnects standards
Owns PHY level Architecture study and recommends system-level design trade-off aligned to IP/SoC requirement and roadmap.
Collaborate across functional teams - Logic, Circuit, Verification, Structural Design in PHY level definition meeting Best In Class Power, Performance and Area metrics.
Collaborate with SoC integration teams on PHY level requirement and integration issues.
Mentor and develop technical leadership pipeline.
Experience in PHY Architecture, Circuit/Logic Micro-Architecture definition of High Speed Memory Interfaces example DDR, LPDDR, GDDR, or On-Package Interconnect IO interfaces, Ultra Low Power Die-to-Die IO, PCIe, Serdes. Design achieved production in high volume and extensive exposure on post-silicon debug and Hardware and Firmware based PHY training algorithms
Hands-On Experience in high speed design building blocks for High Speed Interfaces, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC
Understanding of LPDDR/DDR/GDDR JEDEC specifications and related Memory Interface Protocols
Knowledge of DFI based Memory Sub-systems, Power/Performance optimization and Package/Platform trade-offs is required.
PHY Architecture knowledge needs to span multiple domains (Analog, Digital, Platform Electricals, etc.)
Understanding of design for yield and exposure to production challenges in latest technology process nodes.
Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training and Architecture specification documentation.
Strong written, oral communication and presentation skills
- Bachelor of Science degree with at least 15+ years additional experience, or a Master of Science degree with at least 10+ years additional experience, in Computer Science, Computer Engineering, or Electrical Engineering.
Inside this Business Group
US, California, Santa Clara
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....