Intel Sr. Graphics Hardware Verification Engineer in Folsom, California
Conducts analysis, interpretation, and assessment of hardware architectural specifications defining feature requirements for 3D Graphics blocks.
Defines and develops microarchitecture specifications, logic designs, and HDL code for 3D Graphics blocks.
Designs implementations that meet functional and performance requirements, physical/structural design constraints timing, area, power, as well as proprietary design rules and other quality criteria.
Defines and develops test plans, verification environments, validation components bus functional models, trackers, checkers, scoreboards, test benches, etc., functional coverage points, assertions, random and directed tests, random test constraints, etc. to validate 3D Graphics blocks at various levels of integration.
Integrates and maintains of HDL models and verification environments for simulation and ASIC logic synthesis.
Executes and debugs hardware simulations achievement of functional test coverage objectives.
Identifies and closure of design and environment defects, including bug fixes requiring manual ECOs gate-level netlist edits.
Characterizes and analyses of performance and power results implementation of corresponding design modifications and optimizations as required to achieve power and performance targets.
Executions of ASIC logic synthesis flows implementation of corresponding design modifications and optimizations as needed to achieve timing and area objectives.
Debugs of graphics hardware in emulation and/or silicon hardware environments working with synthetic low-level tests as well as with stimulus from real-world applications and benchmarks and the graphics driver.
BS Degree in Electrical and/or Computer Engineering, or other related field
3+ years of relevant experience with a Bachelor's Degree, or 2+ years with Masters
Working knowledge of computer architecture/organization fundamentals
Knowledge of programming in languages such as: C/C++ or Python; Scripting in programming languages such as Perl
Prior experience with logic design implementation and verification using (coding in) hardware description (HDL/RTL) and verification languages such as Verilog or System Verilog; applying good coding style
Familiarity with definition and development/implementation of verification (simulation) environments, validation components, and tests
Prior experience with usage/execution of logic simulation tools and environments; familiarity with broader ASIC development flows; hardware/hardware model debug
Experience with Unix and/OR Windows OS usage
Familiarity with 3D Graphics architecture concepts, APIs, and standards - e.g., Direct3D, OpenGL; media/video codec standards; implementation of vector-based DSP/SIMD algorithms; Intel CPU architecture
Knowledge of Coverage-based validation concepts and application - functional coverage points, assertions, random and directed tests, random test constraints, etc. using System Verilog or similar verification languages/tools; UVM/OVM verification methods
Experience with Synopsys ASIC design tools - VCS simulator, Verdi, Design Compiler, IC Compiler
Familiarity with formal verification methods - formal property verification (e.g., Jasper), high-level/algorithmic formal equivalence checking (e.g., HECTOR)
Familiarity with digital hardware emulation and hardware debug tools - emulators, logic analyzers, etc.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
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