Intel Design Reliability Methodology Lead in Hillsboro, Oregon

Job Description

Design Reliability Methodology Lead is responsible for defining and developing Intel-wide design reliability methodologies and requirements to enable circuit reliability simulation and design reliability verification execution for IP and SOC design teams.

Additional deliverable is to enable development of reliability CAD development efforts. Expected deliverables are analysis and optimization of design methodology from early detection, verification and correct-by-construction.

Evaluating/assessing design performance/area trade-off/efforts with reliability also is one of the deliverables.

This leader will be partnering with key internal design methodology and execution teams. Also this leader will be engaged in identifying strategic technical challenges and solutions for design reliability.

Qualifications

BS + 9 yrs. exp.; MS + 6 yrs. exp.; /PhD + 4 yrs. exp. in Electrical Engineering with 5+ years of hands-on custom and/or ASIC design experience with building or assessing design reliability.

Knowledge in key CAD tools/methodology circuit sim, PV, noise for custom and SOC design flows is required.

Proven Project Management/ leadership skills in driving development and problem solving are needed.

Device physics/circuit aging/ reliability physics/models as well as skills in statistical data analysis are preferred.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

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