Intel IP Structural Design Engineer in Hillsboro, Oregon

Job Description

Are you thinking about where to build your career? Do you want to join a premier organization and collaborate with the best minds in the world?

SDG’s Shared IP team which integrates analog and digital circuits to deliver solutions to various SOCs that goes into Intel’s amazing products, is actively seeking SoC Design Engineers for one of its team.

In this role, you will oversee definition, design, verification, and documentation of IP development for SoC . You will contribute to the development of multidimensional designs involving the layout of complex integrated circuits, perform all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to craft a design database that goes into a part ready for manufacturing. You will analyze equipment to establish operation infrastructure, conducts experimental tests, and evaluate results.

Please be informed that Intel is proactively trying to find candidates for a position and that may, or may not, be available for all location(s) at this time. If you're interested in this position, we encourage you to apply, and our hiring team will be glad to contact you if/when relevant.

Qualifications

One, or more, position(s) may require the following minimum qualifications for IP Structural Design Engineer(s)

  • BSEE, BSCS, BSCE, or related degree (advanced related degree is preferred.

  • 5+ years of experience (ex. in physical design convergence from logic synthesis to layout verification). Experience with one or more of the following: Synopsys/Cadence SoC design tools, flows and methodology, ICCDP, Design Compiler, IC Compiler/ICC, Primetime, clock tree synthesis.

  • Programming experience in at least one, or more, of the following: VCS, VHDL, Verilog, SystemVerilog, TCL, Perl, Python

One, or more, position(s) may require the following minimum qualifications for IP Structural Design Engineer(s)

  • BSEE, BSCS, BSCE, or related degree (advanced related degree is preferred)

  • 1+ year of corporate or educational experience (ex. in physical design convergence from logic synthesis to layout verification). Advanced related degree is preferred.

  • Experience with one or more of the following: Synopsys/Cadence SoC design tools, flows and methodology, ICCDP, Design Compiler, IC Compiler/ICC, Primetime, clock tree synthesis.

  • Programming experience in at least one, or more, of the following: VCS, VHDL, Verilog, SystemVerilog, TCL, Perl, Python

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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