Intel PCIe-IO Architect in Hillsboro, Oregon
The Scalable Coherent Fabric Architecure Group provide architecture for the coherent fabric and I/O subsystems of Intel’s Xeon processors and derivative products. The PCIe-IO Architect will be responsible for the architecture of processor I/O subsystems and IP’s, should exhibit strong problem solving, and written/verbal communications skills.
Your responsibilities include but are not limited to:
Develops innovative solutions for new problems and/or develops innovative improvements to existing solutions.
Identifies, analyzes and resolves sub-system and/or SoC design and architecture weaknesses.
Determines, specifies and evaluates the viability of complex hardware features and structures, and ensures that software and hardware designs interface correctly.
Influences the shaping of future products by significantly contributing to the architecture used across design families.
Creates documentation to capture hardware architecture for the benefit of SoC design teams and supports these SoC design teams in their implementation efforts.
Bachelor’s degree in Computer Engineering or Electrical Engineering
4+ years of computer architecture in general and I/O architectures experience such as PCIe
Experience with design, validation, and performance analysis tools
Master’s degree in Computer Engineering or Electrical Engineering
3+ years of direct experience with PCIe device or host architecture
Experience/knowledge of multiprocessor cache coherency
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
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