Intel Physical Design Engineer in Hillsboro, Oregon

Job Description

Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.

Physical Design Engineer will support Automatic Place and Route (APR) studies to help drive the process and design improvements for power, performance and area (PPA) metrics. The Design Engineer will engage in performing early design works on selected SoC partitions, recognize potential process and design issues within the design system, implement solutions and drive improvements through data based proposals.

The ideal candidate should exhibit the following behavioral traits:

  • Strong communication and documentation skills.

  • Desire to work in fast pace, dynamic environment.

  • Ability to effectively switch context between multiple projects in a deadline driven environment while keeping track and communicating clearly about project progression.

Candidate must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.


Minimum Qualifications:

  • The candidate must possess a Master's degree in Electrical Engineering or Computer Science field.

  • Candidate must have 1+ years of work or educational experience in math, ability to solve complex problems, digital VLSI circuit design with basic knowledge in synthesis, physical design, performance, power and area optimization.

Preferred Qualifications:

  • Proficiency in C/C++, Perl, TCL, Shell Scripting

  • Experience with industry standard Automated Place and Route tools.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.