Intel Physical Design Engineer in Hillsboro, Oregon
For EyeC Radar development activities we are looking for physical design engineer to work on mmWave RF layout. The Physical design engineer creates bottoms up elements of chip design including but not limited to FET, cell, and block level custom layouts, FUB level floor plans, abstract view generation, RC extraction and schematic to layout verification and debug using phases of physical design development including parasitic extraction, floor planning, full chip assembly, packaging, and verification.
Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, executes and verifies complex chips development and execution of project methodologies and/or flow developments.
BS in Electrical engineering or Computer engineering with focus on HW design.
3+ years' experience in the following areas:
Development of RF and analog layout in advanced processes.
Development process from circuit design to full TO.
Experience with Cadence Virtuoso layout suite required.
Experience with Mentor Calibre Verification.
RF layout methodologies and tools.
Extensive knowledge and practical application of methodologies, physical design and custom RF layout experience.
MS in Electrical engineering or Computer engineering with focus on HW design.
Inside this Business Group
EyeC Radar: The EyeC organization is working on delivering innovative products for Autonomous vehicles that enable true redundancy for safety and a more comfortable driving experience.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....