Intel Senior Core Timing Lead in Hillsboro, Oregon

Job Description

Component Design Engineers are responsible for the design and development of electronic components.

Responsibilities may include:

  • Design of chip layout circuit design, circuit checking, device evaluation and characterization

  • Documentation of specifications, prototype construction and checkout

  • Modification and evaluation of semiconductor devices and components

  • Performing developmental and/or test work

  • Reviewing product requirements and logic diagrams

  • Planning and organizing design projects or phases of design projects

  • Responds to customer/client requests or events as they occur

  • Develops solutions to problems utilizing formal education and judgement

As a Senior Core Timing Lead, your responsibilities include, but will not be limited to:

  • Building a high-confidence plan for core-level timing convergence of an aggressive high frequency design

  • Analyzing core timing at a micro-architectural level by developing a high-level understanding of the core pipeline

  • Coordinating across domains such as micro-architecture, DFx, SOC Integration, Clocking, etc.

  • Defining core timing convergence methodology to support convergence across voltage domains, clock domains, and PV points

  • Influencing program direction with technical proposals, analysis and recommendations

  • Leading and mentoring junior technical staff members.

As an ideal candidate you exhibit behavioral traits that indicate your:

  • Ability to use sound methods and data to test new ideas as well as the desire to have your own ideas be challenged by others

  • Ability to develop an implementation plan, monitor key indicators, and adjust resources and scope to deliver value on schedule

  • Motivation to teach and mentor junior team members to become the rock-stars of tomorrow

  • Strong verbal and written communication and collaboration skills

Qualifications

Minimum Qualifications:

Bachelors in Computer Engineering, or Electrical Engineering with 9 years of relevant work experience or M.S. in Computer Engineering, or Electrical Engineering with 6 years of relevant work experience

Demonstrated success in one or more of the following areas:

  • Ownership of timing integration for a complex project from planning through execution

  • Experience weighing various trade-offs at the integration level, including timing, power, area, and complexity

  • Applied circuit/logic design knowledge in support of timing convergence

  • Tackling deep submicron and high speed design challenges, including process effects across a large dynamic voltage range, aggressive clock network design, and process variation

  • Experience with industry standard integrated circuit design and integration tools, including static timing analysis, floor planning, and design closure

  • Scripting in an interpreted language, minimum TCL in addition to at least one other e.g. Perl, Python, Ruby

Preferred Qualifications:

  • Experience with timing convergence on a high-speed Core IP

  • Research publications, patent filings, or other evidence of personal technical innovation in CPU/Microprocessor design

Inside this Business Group

The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.

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