Intel Senior SOC DFX Engineer in Hillsboro, Oregon

Job Description

The HPC/AI/Custom HAC CPU team of the Scalable Performance CPU Development Group SDG is searching for an energetic and passionate DFx engineer to be part of a DFx team to deliver high quality products.

You will focus on architecting DFT solutions for highly complex chips, design and implementation of DFT features, DFT verification and delivering high quality tester patterns.

The HAC group is responsible for delivering the next generation High Performance Computing Processor for Supercomputers, AI/Machine Learning SOCs, as well as custom ASICs to partner with Xeon processors.We are looking for someone with passion for DFX and experience in dealing with complex problems. Experience with working in a team environment is a plus.

Work experiences includes:

  • Defining DFX methodology for large SOC chips, implementation and verification.

  • Working in collaboration with design, implementation and DV teams to ensure DFX features are implementable.

  • You also understand that relationships formed with other peers, teams, and organizations is key to success in SoC, package and system level test.

Direct Responsibilities:

  • Design, implementation and verification of DFx features on SOC.

  • Work with design verification DV team to enhance DV environment for DFX verification and validation.

  • Work with implementation team to develop timing constraints for DFX logic.

  • Work with manufacturing team to generate tester vectors.

The ideal candidate will be able to demonstrate the following behaviors:

  • Ability to work effectively with both internal and external teams & customers is expected.

  • Strong problem solving skills and a team player.

  • Strong written and verbal communication skills.

  • Facilitator of direct and open communication, diversity of opinion, and debate.

Qualifications

Minimum Requirements:

BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 10+ years of relevant experience in SOC/Package/Board debug and test or MS degree with 7+ years or PhD with 3+ years of relevant experience.

Candidates must have the following:

DFX implementation experience on complex SOC and/or IP. Practical experience with the following DFT features:

  • Scan and compression design and validation

  • Clocking schemes and timing constraintsoIEEE 1149.1 JTAG and TAP controller

  • MBIST design, implementation and verification

  • LBIST design, implementation and verification

  • Experience in debug and test of silicon based products.

  • Must have gone through complete process of generation and debug of test vectors on a tester

  • Some experience with designing/dealing with manufacturing test requirements.

  • Ability to work as an individual and as part of a team to deliver a product which is debug and test friendly starting from the creation of the spec, design, verification, and finally to productization.

  • Ability to deal with DFx integration of complex IP's from different sources onto the same piece of silicon.

Preferred Skills:

  • Experience with Mentor BIST and SCAN insertion tools or equivalent.

  • Experience with design for test and debug, at silicon and board level.

  • Experience with pre-silicon validation.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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