Intel SoC Design Engineer - Design for Test/Debug (DFT/DFD) in Hillsboro, Oregon

Job Description

Come join Intel's Silicon Engineering Group organization as an SOC Design for Test Engineer. As a member of the product team, you will work first hand with multi-function teams/sites, implementing state-of-the-art design in test solutions appropriate for any new and existing technology put into the product. In this role, you will work on front-end RTL DFT design, and you will also have the opportunity to architect new capabilities with the goal of reduced test time, increased coverage, and high design quality. Your focus could be in the areas of Test control, Memory BIST, SCAN logic, Analog testing, or other DFT-related specialties. Additionally you will be asked to pioneer test flows, publish architectural specs, and support next-generation silicon enabling on test/system platforms.


Minimum Qualifications:

  • BS or MS in in Electrical Engineering, Computer Engineering, or Electrical & Computer Engineering

  • Minimum 4 years' experience with design principles and techniques in at least two of:

  • Micro-architecture definition

  • RTL development

  • Validation development

  • Post-silicon test

Preferred Qualifications:

  • Minimum 6 years' experience in any of the above areas

Inside this Business Group

The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

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