Intel SoC Design Engineer – Memory Controller or Mixed Signal Validation in Hillsboro, Oregon

Job Description

Come join Intel's Silicon Engineering Group organization in Pre-Silicon Validation. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs.

Your responsibilities will include but not be limited to:

  • Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide

  • Learning the architecture and microarchitecture by debugging failures to the root cause

  • Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design

  • Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution

  • Developing tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible

  • Developing debugging tools and software

Additional responsibilities for Memory Controller

  • Validation of a Memory Controller IP, either directly or at the system level

Additional responsibilities for Mixed Signal –

  • Functional validation of products with both analog and digital components in them using digital and mixed signal simulation tools


  • Bachelor of Science or Masters of Science in Computer Science, Computer Engineering, or Electrical Engineering

  • 3+ years of experience with reading and interpreting technical specs and Register Transfer Level (RTL) code

  • 3+ years of experience working on IP or SoC development, verification, or integration using Verilog/System Verilog/OVM/UVM3+ years of experience writing validation plans and software to implement those validation plans

  • 1+ years of experience with UNIX* or Linux*

Memory Controller Only

  • 3+ years of experience with memory controller or memory PHY development and verification

  • Knowledge of JEDEC DRAM protocols such as DDR4 and LPDDR4

Mixed Signal Only

  • 4+ years of experience with basic analog, mixed signal circuits

  • 4+ years of experience with mixed signal simulation tools like Discovery AMS / Cadence AMS or circuit simulation tools like Pspice and application of circuit analysis concepts

Preferred Qualifications

  • 1 year experience with computer architecture

  • 1 year experience with IA-32 assembly and/or Verilog* programming experience

  • 3 years of experience with validation or testing experience, especially in a silicon design team

Inside this Business Group

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....