Intel Physical Design Engineer in Hudson, Massachusetts
Do you want to collaborate with the best minds in the world? Do you love the idea of directly impacting Intel's future generation CPUs? Can you bring your high performance CPU design experience and help Intel reach the next level? Are you experienced in design implementation in state of the art process technologies?
We are a trusted, creative SoC design team delivering Xeon products and related IP's for the Server markets. The Scalable Performance CPU Development Group (SDG) is building the next generation of CPU's that fuel Intel's growth in Data Center and will make a significant impact to the "virtuous growth cycle." SDG is looking for an extraordinary physical design implementation engineer to join our elite engineering team.
You will collaborate with architects and logic designers in evaluating implementation details of complex design features. You will support all facets of the SoC design flow from high-level design through synthesis, place and route, timing analysis and power reduction. You will be a key contributor for building a design database that has completed sign-off flows and is ready for manufacturing.
Your responsibilities will include but not be limited to:
IP Family and/or block-level floor planning
Power supply and power grid planning and analysis
Logic synthesis of design blocks
Formal Equivalence Verification (FEV)
Clocking network planning and analysis
Auto Place-and-Route (APR) using Synopsys ICC tools
Timing verification using Synopsys PrimeTime
Physical verification - Layout vs. Schematic (LVS), Design Rule Checks (DRC), Electrical Rule Checks (ERC), and Design for Manufacturability checks (DFM)
Debug and resolution of integration issues at parent level
Completion of design reviews and design signoff flows
Assist in the preparation of the full-chip layout design database for introduction to manufacturing
Bachelors in Electrical Engineering, Computer Engineering, Computer Science or related
6+ years of experience in Physical Design or Design Implementation
Experience with Synopsys design tools, flows and methodology using ICCDP, Design Compiler, ICC/ICC2
Experience in Static Timing Analysis
Experience with TCL or Perl programming
Preferred (Additional) Qualifications
Masters in Electrical Engineering, Computer Engineering, Computer Science or related
Experience in RTL/Logic design
Experience in Layout verification and developing DRC cleanup scripts
Experience in circuit design
Experience in computer architecture
Experience in Python, C and/or C++ programming
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
US, California, Santa Clara
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