Intel SoC Frontend Design Automation Engineer in Hudson, Massachusetts

Job Description

In this position you will be working within the Product Development Solutions PDS organization, developing and supporting a ground breaking custom high performance SOC. This is a great opportunity to join the front-end design team in a Design Automation role, early in the product lifecycle, as we enter the technology readiness TR phase, then move into design and execution EXE.

As an experienced Integration Frontend Design Automation Engineer, you will be responsible for:

  • Drive the RTL integration methodology, innovations and productivity improvements in design flow while focusing on all aspects on integration including low power, IP requirements, RTL integration flow, and physical design readiness

  • Work with a team of talented engineers in the tools team and SoC/IP design teams

  • Drive methodology, innovations, and productivity improvements in design flows while working with vendors on feature development and bug resolution.

  • Develop and test Engineering Design Automation tools, creates flows/scripts to analyze, and test design methodologies

  • Evaluates vendor practical capabilities to provide required products or services

  • Design, deploy, and test efficiency of tools to utilize in achieving design goals and collaborating with design teams on methodology development

  • Own front line support for one or more tools and be part of a very strong and productive design automation team

  • Advocate in applying design methodologies to help execute projects effectively and successfully with high quality

The ideal candidate will be able to demonstrate the following behaviors:

  • Ability to work effectively with both internal and external teams/customers

  • Ability to mentor other engineers and technically guide them

  • Capable of working in a high performing team to deliver the results required from the organization

  • Facilitator of direct and open communication, diversity of opinion, and debate

  • Possess strong communication and team work stills

  • Possess strong inter-personal skills influencing strategic planning, engineering, customers, and management

  • Experience supporting big and small team projects will be a plus

Qualifications

Minimum Qualifications

  • BS or MS in Electrical Engineering, Computer Engineering, or Computer Science

  • 5+ years of experience in RTL/Logic design on ASIC's or IP blocks or SOC's using System Verilog RTL coding.

  • Experience with RTL Design Methodology, Gatekeeper, GIT, VCS, CDC, Synthesis etc.

  • Experience writing System Verilog

  • Programming experience in C++, any Shell scripting (Perl, tcl) and Assembly Algorithms and digital logic

  • Experience with a range of 3rd-party logic design tools

Preferred Qualifications

  • Experience in Logic Design and RTL development and Integration

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Other Locations

US, California, Santa Clara

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