Intel SOC Physical Design Engineering Manager in Hudson, Massachusetts
In this position you will be working within the Server Development Group (SDG), developing a ground breaking high performance custom SOC. This is a great opportunity to join a talented team, early in the product lifecycle, as we enter the technology readiness (TR) phase, then move into design and execution (EXE). This program will include innovation in system to achieve performance across a broad scope of system components including computing (core/un-core), interconnect (on-die, on-MCP, off-MCP), silicon technologies, packaging, reliability and system software.
As a manager, you will set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance.
You will lead the SoC design team whose responsibilities include Subsystem and IP design, full chip floor-planning, power grid design, clock tree design, synthesis and timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification DRC/LVS/Antenna.
Troubleshoot a wide variety of physical design complex issues and apply proactive intervention.
Opportunity to work closely with the RTL designers to ensure the design is balanced and optimized from timing closure & design routability perspective.
Oversees definition, design, verification, and documentation for SoC System on a Chip and subsystem/IP development.
Selects, develops, and evaluates SoC and IP design engineers to ensure the efficient operation of the function
Degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 10+ years of industry experience in SOC/IP physical design. You will have
experience managing engineers and leading a team, including:
Demonstrable experience in all aspects of SOC and IP physical design
Experience setting objectives and goals, schedules, and staging plans
Experience tracking execution progress and enabling the team.
Experience in performance management.
Demonstrable experience in floor planning and routing
Demonstrable experience in physical design convergence and tape-in
Circuit design and feasibility
Interconnect design and analysis
Layout design understanding
Strong written and verbal communication skills
Strong analytical ability and problem solving skills
Ability to work effectively with both internal and external teams/customers is expected.
Ability to mentor other engineers and technically guide them.
Ability to work independently and at different levels of abstraction
Capable of working in a high performing team to deliver the results required from the organization.
Experience working with Contingent Workers.
Facilitator of direct and open communication, diversity of opinion, and debate.
This is an Intel Federal Position
This position involves work on a U.S. Government contract which may impose certain security requirements. The government may require that you certify your citizenship status. If you are not a U.S. citizen, the government may require you to pass a security check before you can be approved to work on the project. Please note that any offer by Intel for this position is conditioned upon meeting and/or passing the U.S. Government's security check requirements should the government impose these requirements.
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