Intel ARM Subsystem Design Eng in San Jose, California
As a manager, set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance. Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Selects, develops, and evaluates SoC design engineers to ensure the efficient operation of the function.
Write RTL code that can efficiently interface the ARM Cortex subsystem
Write test benches to verify the code
Design for reusability; the RTL should be flexible, parameterized, well documented and supported
Train customers and Applications Engineers on the use and integration of the IP
Develop a set of metrics to assess the performance (power, throughput, latency) of the integrated ARM subsystem core in different use cases
Create a set of use cases and develop specific IPs to simplify integration of the subsystem; document the advantages of each scenario and define a selection method for the most optimal based on the customer system requirements
Work closely with the Customer Engineering Team and create Application Notes and Tutorials to introduce customers and internal teams on the ARM Subsystem usage
Architect and develop fully configurable IPs and extend the IP Cores library with qualified cores meeting the required performance/area metrics
Create a testchip to validate all the use modes of the ARM Subsystem including the IP Cores as part of the eASIC Platform Validation
Required Education and Experience
• BSEE required; MSEE preferred
- Minimum 8 of experience in Design, Verification, Synthesis of ARM-based subsystems
• Knowledge of chip design and implementation flow
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....