Intel Senior ASIC Design Engineer in San Jose, California

Job Description

About this position...Come and join us! Intel is seeking a highly qualified candidate to join our Data Center Group DCG team as a Senior Logic Design Engineer Packet Processing!

In this position, you would be joining an innovative team that designs and builds the hardware, software and networking technologies that power the infrastructure of the leading datacenters in the world.

Our organization works on all levels of ASIC development, spanning high-level architecture, to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team as a Senior Logic Design Engineer.

As a Senior Logic Design Engineer you will...

Use your knowledge of specifications, mathematics, and computation to write efficient and elegant RTL to implement components of complex networking ASICs.

This is a senior role requiring participation through the full life-cycle of the program, from developing micro-architecture specifications, RTL implementation, unit verification, timing convergence, ECO implementation, debug analysis and reviews.

Qualifications

The ideal candidate should exhibit the following behavioral traits: -

  • Thoughtful and perceptive analytical ability.

  • A genuine curiosity for understanding the complete system.

  • Dedicated to creative problem solving-.

  • Ability to work independently and at various levels of abstraction.

  • Committed to getting things done and executing to plan

Minimum Qualifications:

  • B.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.

  • 4+ years of experience in System Verilog based logic design or verification, in deep submicron technologies.

  • Familiarity with Ethernet and other networking protocols.

  • Familiarity with packet processing concepts.

Preferred Qualifications:

  • 7-10 years of experience in digital design on multiple networking ASICs.

  • Extensive experience with Ethernet, TCP/IP, MPLS, tunneling and other networking protocols.

  • Extensive experience with packet processing architectures packet parsing, ACLs, p4 language, scheduling, policing, etc.

  • Experience achieving timing closure on high performance ASICs, in deep submicron technologies.

  • Experience with low power design techniques, power estimation methods, clock domain crossing techniques.

  • Experience using OVM/UVM and coding SystemVerilog assertions and coverpoints.

  • Experience with scripting languages, such as Python or Perl.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

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