Intel Xeon + FPGA Acceleration Solutions R&D Director in San Jose, California
The Programmable Solutions Group at Intel is building heterogeneous accelerator architectures with FPGAs. The Xeon + FPGA group is responsible for combining Intel’s world-class Xeon processors with flexible, programmable FPGAs that can accelerate the performance of workloads typically run in the Data Center and Edge by orders of magnitude.
We are seeking an R&D Director to lead our team in delivering the next generation of Xeon + FPGA accelerator platforms. These platforms include coherently attached FPGAs and discrete FPGA accelerator cards, highly optimized RTL to deliver high-performance IO connectivity to Xeon processors running Intel’s open-source OPAE software acceleration framework. Solutions built on this technology cover genomics, deep-learning, data analytics, network function virtualization, and other fast growing areas.
Management experience including:
• Management of medium sized groups 40 or more.
• Proven hiring track record (ability to recruit and retain).
• Clear, actionable, and proven development strategies enriching staff and team efficacy.
• Established long-term record of project planning and execution.
• Providing technical guidance to product planners, marketers, business owners etc.
• Effective communication skills, presenting internally, at technical conferences, trade shows, and customer discussions.
Experience with Virtualization technologies: Hypervisors, SR-IOV, direct pass-through, etc.
Experience writing with C or similar languages.
Experience with OpenCL, CUDA, or similar.
Experience with UPI coherence on x86 and knowledge of other coherency architectures.
Experience managing software build methodologies and frameworks (Agile, regression testing, automated build and continuous integration, test triaging and bug resolution)
B.S. (M.S. preferred) in Computer Engineering, Computer Science, or equivalent.
7-10 years FPGA-centric development experience including:
Digital Design using Verilog, VHDL, or equivalent
Synthesis, Place and Route, Advanced Timing Closure, and Floor Planning.
Digital design debug using common simulators (ModelSim, VCS, etc.)
FPGA debug using SignalTap or similar tools.
Server system SW/HW development
Background in microarchitecture including:
Memory subsystems, shared virtual memory, and memory coherence
IO technologies including PCIe, DDR, storage and networking (MAC/PHY)
CPU basic operation and classic acceleration techniques (GPGPU, ASICs, etc.)
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
US, Oregon, Hillsboro
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Position of Trust. This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Talent Consultant.