Intel Big Core Memory/Register File Design Engineer in Santa Clara, California
In this position, you will be responsible for the structural design in DDG Big Core CPU design team. Your responsibilities will include but not be limited to: performing all aspects of the Memory/Register File and VLSI circuit design flow from high-level design to circuit schematics, cell placement, static timing analysis, power, layout/area optimization to create a design database that is ready for manufacturing. Also, it is required to write some scripts to improve data analysis and productivity.
- BS/MS degree in Electrical Engineering (EE), Computer Engineering (CE), or other engineering/applied sciences degree, 4+ years of related experience with a BS Degree OR 3+ years of related experience with a MS.
-BS candidates, must have the unrestricted right to work in the US without requiring sponsorship.
4+ years hands-on experience in Memory/Register FIle design - Register File, VLSI circuit design, place and route, static timing analysis, low power design, and layout design
Strong engineering, problem solving and analytical skills
Strong verbal and written communication skills
Ability to work well in a highly dynamic, cross-geography collaborative environment
Experience in writing and producing software code using languages such as PERL and TCL
Knowledge in Unix/Linux operating systems
Knowledge of CAD physical design software
Inside this Business Group
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....