Intel DFT & Automation Manager in Santa Clara, California

Job Description

  • DTEG is Intel’s cross-team DFT group, driving DFT architectures, methodologies, and automation across Intel.

  • DTEG is looking for a strong leader to be manage the Santa Clara DTEG team and lead DFT domains.

  • In this position you will be part of DTEG engineering management team, responsible for driving DFT improvement and convergence across SEG engineering teams.

  • As a DFT manager you will be responsible for execution of DFT architecture/methodologies and automation supporting those methodologies.

  • In addition to managing, you will be responsible for setting technical direction in one or more areas, such as Scan, Array test, TAP or DFT automation.

  • As a manager, set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance.

  • Determine DFT architecture design and logic design and influence Intel’s post-silicon engineering teams.

  • Select, develop, and evaluate DFT engineers to ensure efficient operation


  • Bachelors, Masters, or Ph.D. in Computer Engineering or related field.

  • Background in DFT in silicon design teams

  • Preferably background in automation, especially DFT automation.

  • Leading and building teams through setting goals, schedule and staging plans along with tracking and enabling execution for team.

  • Strong skills in influencing and collaborating with multiple teams across Intel

Inside this Business Group

Other Locations

US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.