Intel Digital Design Engineer in Santa Clara, California
Intel is developing a custom-designed SOC optimized for deep learning. You will be a key part of a silicon design team chartered with creating silicon IP and ASICs targeted at state of the art Deep Learning and Machine Learning algorithms. Your responsibilities include architecture, RTL design, debug, and support for validation and silicon bringup.
Be able to take design from concept to microarchitecture
Design RTL/Logic on ASIC, IP blocks or SOCs using Verilog/SystemVerilog
Analyze micro-architecture trade-offs and provide clear documentation
Implement low-power design using UPF and clock gating
Simulate and debug logic and deliver high quality designs
Support silicon validation and silicon debug
BS in Electrical Engineering, Computer Engineering or a closely related field of study with 9 years of industry experience
5+ years of relevant experience in digital design
Good knowledge in languages relevant to the ASIC development process including Verilog and SystemVerilog
Experience with scripting in either Perl or Python is preferred
Inside this Business Group
Intel AI, leveraging Intel's world leading position in silicon innovation and proven history in creating the compute standards that power our world, is transforming Artificial Intelligence (AI) with the Intel AI products portfolio. Harnessing silicon designed specifically for AI, end to end solutions that broadly span from the data center to the edge, and tools that enable customers to quickly deploy and scale up, Intel AI is inside AI and leading the next evolution of compute.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....