Intel DSP SerDes Architect in Santa Clara, California

Job Description

We are looking for dynamic leaders who can develop and drive technical solutions with our customers so that we grow our market share and contribute to Silicon Photonics Solution Group's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. Intel Silicon Photonics Product Division SPPD is at the forefront of silicon photonics integration. Since announcing the world's first hybrid silicon laser nearly a decade ago, our team continues to lead the industry with cutting-edge technology and efficient, scalable high-volume manufacturing. Our dedication to advanced development ensures that Intel Silicon Photonics continues to drive future data center bandwidth growth with smaller form factors and higher speeds, from 100G today to 400G and beyond tomorrow. We are looking for great talent to accelerate this journey, so if you are interested in joining our leading organization, then we want to hear from you!. The DSP SerDes Architect's main role is to architect and design of digital signal processing DSP and forward error correction FEC hardware for next-generation optical transceivers


ResponsibilitiesDevelop channel models and run simulations to help define SerDes architecture. Develop models C, Matlab, etc. and perform detailed performance analysis of DSP and FEC algorithmsCreate DSP/FEC hardware block specifications appropriate for RTL implementationDevelop MATLAB and C/C++ system models for simulation and verificationDevelop and run system level simulation to evaluate architectural tradeoffsDefine and document signal processing block requirements, architecture and lab test planWork with design team to perform bit true match for RTLLab testing and debug

Minimum Qualifications

PhD in electrical engineering or equivalent field, or MS with 3+ years experience. Experience in the design of the Mixed-Signal or DSP based multi-Gb/s SerDesExperience, projects in or familiar with physical layer algorithms and standards, in the field of SerDes, Expert knowledge in Communication Theory and Digital Signal Processing algorithms.Solid background in optical communication inclusive of optical modem design with familiarity with advanced modulation formats, FEC, constellation shaping, nonlinear compensation, TX pre-compensation and techniques to enhance modem performanceHigh performance carrier phase recovery algorithms for high order modulation formats. Good understanding of how DSP algorithms map onto efficient hardware designs. Physical layer digital optical communications, modulation and transmission system engineering. Must have demonstrated proficiency with C/C++ and MatlabGood communication skills and capable of independent work with guidance

Preferred Qualifications

Understanding in analog/digital circuit implementation, modeling is strongly desiredExperience in firmware design and implementation is a very big plus. Experience in system performance test and validation is desired. Experience in designing high-speed Clock and Data Recovery CDR PLLs and DFE is a plus.Knowledge of IEEE 802.3 10G/25G/50G Serdes is a plusWorking knowledge of Transmission line theory and s-parameter is a plus

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.