Intel Emulation Engineer in Santa Clara, California

Job Description

Creates emulation/Field Programmable Gate Array FPGA models from a Register Transfer Level RTL design using emulation/FPGA synthesis, partitioning and routing tools. Defines and documents RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for preSilicon and postSilicon functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to presilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation easeofuse and improvement of equipment utilization.

Qualifications

Required Experience/Skills (Must Have)

  • B.S OR M.S EE/CS/CSE with 10+ years of experience OR a PhD with 7+ years of experience.

  • RTL design or verification experience with fluency with Verilog, System Verilog, C/C++.

  • Familiar with Python, Perl and perform basic coding and debug of SW tools.

  • Prior emulation, FPGA, ASIC experience a bonus.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Other Locations

US, Oregon, Hillsboro

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