Intel Graduate Internship in Santa Clara, California
The Visual Computing Products Group VCP and the Intel Parallel Computing Lab PCL are looking for a graduate intern to help add support for spatial architectures in the Halide programming language. The temporal-to-spatial T2S project brings new scheduling constructs to Halide that express spatial replication essential for achieving optimal performance on FPGAs. This internship centers around creating a proof-of-concept under the supervision of the T2S project lead and incremental progress reports to the product team. The goal is to create a working prototype that will demonstrate that Halide can radically simplify high-performance FPGA designs.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Relevant experience can be obtained through school work, classes and project work, internships, military training, and/or work experience.
Must be pursuing a PhD in Computer Science, Computer Engineering or related field
Minimum of 12 months of experience with:
FPGA design, debug and/or test experience using HLS/HDL tool
Hands-on experience in compiler design and optimization, a detailed understanding of LLVM.
Experience with high-performance computing using CUDA, OpenCL and/or Metal.
Prior experience with Halide.
Inside this Business Group
The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.
US, Oregon, Hillsboro
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