Intel IP Logic Design Engineer in Santa Clara, California
Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Evaluates new feature requests, Designs and develops IP features. Provides IP integration support to SoC customers and represents RTL team. Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog and integrating other IPs into the design. You will contribute to specifications at multiple levels, including the HAS and MAS micro-architecture spec. You must be able to balance design trade-offs with modularity, scalability, global clocking/power-management and debug requirements, chassis compliance, power, area, and performance. You will provide IP integration support to SOC customers and represent RTL and the IP team.
BS in Electrical Engineering or any other related field with 4+ years of experience in in digital VLSI design OR a MS with 3+ years of experience OR a PhD degree with 1+ years of experience.
Additional qualifications ideally include:
Experience in the following areas/ skills:
Logic design using System Verilog Micro-architecture trade-offs and documentation
Familiarity and experience in PCIe protocols, Cache-coherence protocols, on-chip Interconnect fabrics, Multi-clock domain design, IOSF Sideband and Chassis State machine design.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
US, Oregon, Hillsboro
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