Intel Photonics Physical Design Engieer lead (Mask Design) in Santa Clara, California
Intel's Silicon Photonics Product Division SPPD is seeking a R&D Physical Design Engineer (Layout/Mask Design). We offer you to be part of a creative development team which ambitiously contributes to the shaping and driving of the next generation exciting photonics technology. We are looking for a cutting edge experienced Photonics Physical Design (Layout/mask Design) Engineer with a strong technical background in full custom layout techniques in deep Photonics and/or sub-micron CMOS technologies. Extensive knowledge and hands on experience of top level, block and cell level layout of Photonic designs. Abstract view generation, RC extraction, Layout vs. Schematic (LVS) verification, Design Rule Check (DRC) verifications, ERC verification. Requires expansive knowledge and practical application of layout methodologies and physical design.
Job responsibilities primarily (>90% of the time) include completing layout and mask design projects, partnering with and leveraging Process development and Integration, Designers, DA owners in providing efficient, automated, mistake free, LVS/DRC violation free (clean) mask design. Enable efficient layout's and DR checks for NPI's along with enabling flows and methodologies. Own designing, deploying and testing efficiency of tools to utilize in achieving design goals and collaborating with design teams on methodology development. Advocate applying design methodologies to help execute projects effectively and successfully with high quality.
The candidate should be able to work with limited supervision, has great communication skills and able to lead other mask designers and contract employees as needed in a team environment. Must be able to troubleshoot a wide variety of problems up to and including difficult design issues and apply proactive intervention. Schedules, staffs, executes on time and verifies complex chip development. Strong problem solving skills, ability to multi-task and prioritize tasks. Ability to work in a dynamic environment and highly self-motivated technical leader with high tolerance of ambiguity. Expertise in model based problem solving and completing after action reviews.
Candidate should possess Master's degree in EE/CS or BS with equivalent experience.
6+ years of industry experience and technical layout training in mask design, Cadence Virtuoso layout suite required.
Demonstrated expertise with the Cadence Virtuoso* environment, including Schematic Composer and Layout Editor. Proficient in Virtuoso platform, ADE environment, tech file, streamIn.
Experience with methodologies, Photonics layout and physical design. Experience with both internal and external foundries tape-in/tape out
Thorough knowledge about standards and practices in Physical Design. Experience in identifying and facilitating plugging systemic gaps in design rules, automated DRC.
Background in physical layout, verification and be proficient in layout assignments from upper level layout, floor planning and component level layout.
Very good understanding of Physical Design Verification methodology to debug LVS/DRC issues at both device, block and top levels.
Good understanding of photonic component design. Excellent working ability with circuit design and layout methodologies in a team environment.
Capable of sharing tool knowledge and expertise with other physical designers and contribute to a positive team environment through developing and proliferating best known methods
The position is relevant to an experienced physical design/layout team manager. A proven experienced manager, driving execution as well as effectiveness process improvements. Experienced in the VLSI industry, layout or back-end is important to understand the technical scope of the job.
Good communication skills, both in written and verbal, working with colleagues in other Intel sites.
Working in a challenging, matrixed and dynamic environment and process maturity levels. Capable and willing to contribute to these challenges both in time and good ideas (Open minded).
Frequent travel to various Intel locations may be necessary 25% of the time
Layout design experience for Photonic components such as Modulator, lasers, Photo diodes etc. Hands on foundry experience and expertise in developing Photonic design rules, component libraries, PDK will be strong plus.
Experience leading and develop a sub team of layout designers that has variable level of experience, define and execute challenging layout projects both in time and complexity
Experience in IC Design or Computer Aided Design CAD. Experience in scripting skills, especially TCL and PERL , SKILL, Python a plus.
Experience using Lumerical interconnect, K-layout.
Experience with Circuit simulation flows development, support and debug. Parasitic extraction flows, LVS, DRC, flows setup and debug.
Experience in developing photonics design rules, standardizing design blocks, standardizing front end simulation tools, component libraries, Pcell, enabling effective design automation and design rule checking tools and PDK development for SiP. Electronic Design Automation EDA tools/flows and platforms to ensure high-quality delivery of kit content to customers. Ability to develop, validate/QA and support the custom layout collateral portion of the Optical Process Design Kit PDK.
Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
US, Arizona, Phoenix
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....