Intel Physical Design Engineer in Santa Clara, California
The Scalable Performance CPU Development Group SDG is searching for an energetic and passionate hands on structural design team member to handle physical design tasks from synthesis to closing blocks in P&R and closing the chip for tape-in. As a Physical Design Engineer you will be part of a talented team of engineers that takes designs from RTL to complete physical implementation, in a fast-paced technically challenging environment.We are looking for someone who has passion around improving the way we solve complex problems through the work of the team as well as their own direct contributions. Working experiences include digging in deep on technical challenges, working across and empowering a team to succeed, and fostering technical guidance to other team members in your related fields of expertise.Direct Responsibilities:Performs all aspects of the SoC block level physical design flow: synthesis, block floorplanning, place and route, timing and power, finally physical verification to create a design database to be included in full chip that is ready for manufacturing.Block floorplanning and negotiating for space with fullchip lead, structural design and physical verification of SOC.Determines block floorplan, placing memories and pins in the context of full chip floorplan.P&R and timing closure of block.Close timing with required logic, layout & timing ECO changes.Deal with UPF and power domains in various tools involved in block builds.LEC, EM, IR, noise analysis and fixing.Clean blocks through LVS/DRC/ERC.The ideal candidate will be able to demonstrate the following behaviors:Ability to work effectively with both internal and external teams as well as external customers is expected.Ability to mentor other engineers and technically guide them.Strong problem solving skills Strong written and verbal communication skillsSelf-motivated & driven who can work Capable of working in a high performing team to deliver the results required from the organization. Facilitator of direct and open communication, diversity of opinion, and debate.
- BS degree in Electrical Engineering, Computer Engineering or other related field of study with 3+ years of relevant experience in SOC structural design or MS degree with 2+ years of relevant experience in SOC structural design.
Candidates must have the following:
Strong expertise in the RTL2GDS flow development and design implementation in leading process technologies.
Good understanding of the RTL2GDS concepts related to synthesis, place & route, CTS, timing convergence, layout closure, UPF based power methodology, ECO implementation, power analysis etc.
Experience with Synopsys and/or Cadence physical design tools, i.e. Design Compiler, ICC, ICC2, Genus/Innovus, Mentor Calibre, spyglass, primetime etc used in the RTL2GDS implementation.Well versed with timing constraints, STA and timing closure.
Expertise on high frequency clocking methodologies will be an added plus.
Good automation skills in PERL, TCL.
Proven ability to work as an individual and as part of a team to deliver a product starting from the creation of the spec, design, verification, and finally to tapeout.
Experience with ASIC based designs
Experience with dealing with various type of external interfaces, like DDR, PCIe or similar.
Experience with Intel design flows and/or industry standard ASIC vendor flows.
Experience implementing new flows based on industry standard tools.
Expertise in dealing and designing with complex IP's from different sources onto the same piece of silicon.
Understand system and package implications of the silicon design decisions.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
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