Intel Pre-Si Formal Verification Engineer in Santa Clara, California

Job Description

Scalable Performance CPU Development Group SDG at Intel is looking for a Sr. formal verification engineer to apply formal methods to industrial-scale hardware verification challenges. As a member of the SDG HAC SS Val team, the candidate will work closely with RTL designers, architects, validators and other formal verification engineers.


  • Writing verification plan for a hardware IP or a block design, developing formal proofs to implement the verification plan, reviewing the completed FV proofs with stakeholders, and developing new formal verification methodology for advancing the state of the art In-depth understanding of formal verification principles, methods, and relevant standard industry practices

  • Expertise for applying FPV formal property verification on micro-architecturally complex control logic typically encountered in server micro-processor designs

  • Expertise with applying formal methods to arithmetic data-path verification, arbiters, routers is a significant plus Familiar with the fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs, Familiarity with HDL Hardware Description Language, such as System Verilog and digital logic design

  • Familiarity with industry level FV tools like JasperGold and the apps associated with it like JGCOV, JGAFL, JGSEQ, JGARCH Pre-silicon validation of designs which include processor cores and custom logic

  • Experience with pre-Silicon simulation tool flows required.


Master degree in Electrical/Computer Science Engineering plus 5+ years relevant industry experience OR Bachelor Degree in Electrical/Computer Science Engineering plus 7+ years relevant industry experience Experience in RTL languages - System Verilog or VHDL

  • Experience with digital design and verification methods

  • Familiarity with industry level FV tools like JasperGold

  • Familiarity with pre-si simulation based verification is a must

  • Experience in using Simulation and debug tools include but not limited to:- Synopsys VCS, Verdi and DVE

  • Good Knowledge of UVM including developing verification test benches and constrained random validation.

  • Experience with modern CPU architecture, such as memory cache hierarchy, scheduler, pipeline

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Other Locations

US, Oregon, Hillsboro

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