Intel Senior Analog IC Design Engineer in Santa Clara, California
In this role, the Senior Analog RC IC Design Engineer will be part of team contributing to Silicon Photonics Solution Group's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. As Senior Engineer, the individual will be involved in developing key high speed mixed signal designs from architecture to product. Responsibilities will include driving system specifications, defining circuit architectures and enabling designs meeting power, performance and cost for next generation optical interconnects. As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development. Specify, architect and design low voltage and low power Mixed-Signal integrated circuits from product definition through characterization and qualification. Plan design work with constraints on performance, power, time and quality. Provide guidance to junior designers and layout engineers. Prepare and participate in concept, schematic and final design reviews for circuit blocks. Guidance to develop test plans for lab characterization once design comes back from fab. Document all design work with review materials and detailed design descriptions as well as participate in the writing of datasheets and application notes for customers.
Intel® Silicon Photonics Product Division (SPPD) is at the forefront of silicon photonics integration. Since announcing the world’s first hybrid silicon laser nearly a decade ago, our team continues to lead the industry with cutting-edge technology and efficient, scalable high-volume manufacturing. Our dedication to advanced development ensures that Intel Silicon Photonics continues to drive future data center bandwidth growth with smaller form factors and higher speeds, from 100G today to 400G and beyond tomorrow. We are looking for great talent to accelerate this journey, so if you are interested in joining our leading organization, then we want to hear from you!
The ideal candidate should have MS and 4+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in 180nm, 90nm, 45nm and 28nm.
Experience with design of high speed mixed signal circuits e.g., SerDes, counters, dividers, etc..
Experience with design of Analog RF front end circuits such as Drivers, Trans-Impedance Amplifiers TIA, limiting amplifiers, etc.
Good understanding of low noise PLL, Clocking & data recovery architectures.
Deep understanding of Signal Integrity and Channel modeling.
Experienced with Mixed signal design flow using Cadence and Mentor tools.
Able to characterize silicon in and use equipment such as BERTS, HSO, VNA etc.
Deep understanding of full-chip designs including custom IO and package design.
Familiarity with Optical communications.
Experience in designing circuits for 28Gbps+ operation.
Experience with Modulation techniques such as NRZ/PAM4 SERDES and system standards such as CAUI-4 or OIF-25G-VSR.
Excellent oral and written communication skills.
Deep understanding of RF IC Transceiver architectures, design & tradeoffs
Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.