Intel Senior Design Verification Engineer in Santa Clara, California
Join Intel's newly formed Configurable Fabric Group (CFG) where we develop the core fabric and IP technology to push the boundaries of what's possible in System-On-Chip (SoC) architecture and design.
The position involves architecting and implementing configurable test environment and tests to verify the functionality and performance of the network. This role requires close collaboration with architects and logic designers to come up with test plans and verification completeness metrics.
MS degree in Electrical/Computer Engineering or Computer science
5+ years of experience in pre-silicon chip verification
Experience with System Verilog and methodologies like UVM/OVM
Experience with Intel interface protocols such as IDI, CMI, IOSF and AMBA bus protocols
Knowledge of networking, computer architecture, cache-coherency
Strong Python/Perl programming and clean coding skills
Experience in writing testplans, debugging, and test writing for hardware chip design
Strong problem-solving skills
Good communication skills
Inside this Business Group
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....