Intel Senior RTL Design Engineer in Santa Clara, California
Join Intel's newly formed Configurable Fabric Group (CFG) where we develop the core fabric and IP technology to push the boundaries of what's possible in System-On-Chip (SoC) architecture and design.
The successful candidate will possess detailed understanding of RTL design, verification, synthesis, and low power techniques. Work involves microarchitecture, RTL design and verification, synthesis and timing.
MS degree in Electrical/Computer Engineering
5+ years of experience with details of RTL development using Verilog including:
o Functional and structural RTL design, design partitioning
o Simulation and regression, collaboration with design verification and software teams
o Experience with latest RTL languages and tools, including:
o Simulation tools, synthesis tools and static timing tools
o Experience with the following disciplines is highly desirable:
o System architecture, Intel or AMBA bus protocols, Functional Safety and Cache coherent systems
Inside this Business Group
US, Oregon, Hillsboro
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....