Intel Senior Technical Program Manager in Santa Clara, California

Job Description

The Chipsets & IP Group (CIG) Program Office of Intel Corporation is looking to fill the position of a Senior Technical Program Manager to manage all aspects of the SoC Independent SW Sandbox and IP subsystem integration of Hardware and Software from planning to delivery of virtual tape-in quality sub systems. You will work with multiple IP teams cross discipline, covering IPs not limited to CIG IPs across several SOCs to establish development commitments towards chassis roadmap applied to the SW SBX, a virtual platform system for early SW / Driver development.

You will ensure timely high quality delivery of associated collateral through to production. You will be interacting and collaborating with Planning, Architecture, Sandbox, IP, PSS, HW, SW, Val and other related functions to meet product roadmap requirements and will play an important role in the SOC Independent IP (SIIP) initiative for efficient and high velocity integration of IP Subsystems into SOCs. The position also includes defining and driving requirements and priorities to ensure Intel solutions deliver leadership capabilities, driving delivery of RTL / SIP, Software / Firmware drops, developer kit enabling efforts, and other various deliverables.

You will support multiple SOC projects that range from IOT devices through Servers and simultaneously drive multiple internal IP development efforts. You will drive planning and commitment of CoE IP deliverables to multiple SoC customers and drive coordination between the various IP components. You will work with customers and key stakeholders to identify priorities and provide strategic direction in cooperation with IP / SOC Planning orgs and business units.

The SOC Independent IP Initiative seeks to improve IP architecture content, IP planning/funding cycles, and design PLC timelines (Also for SIIP PLC) so as to deliver IP RTL, HW, SW, and Hard IP to internal chassis standards independent of any specific SOC. The initiative has visibility up through MCM and requires frequent interaction throughout, impacting all business units, IP development, and SOC development organizations. The candidate should be experienced driving technical topics across many organizations simultaneously and reporting to executive management on plans and progress on the same.

Qualifications

Candidate should have a degree in Computer Science, Computer Engineering, Electrical Engineering or related area. Minimum requirement is BS+10 or MS+8 or PhD+6.5 years of Planning/Program Management experience knowledge of Project Management methods and tools involving cross functional teams. A good understanding of IP and/or SOC Product Life Cycles (PLC), SW design PLC cycles, PSS (Pre-Sil) platforms & flows, PSS execution challenges and Platform level skills. Strong knowledge in RTL level Digital IC Design using System Verilog and/or Verilog Experience with languages and standards such as Verilog, System Verilog, UPFExperience with SIP/HIP/SoC standard tools and methodologies Saola, ACE, VCS, HDK, etc. Strong SOC Architecture knowledge with in depth understanding of sandbox and chassis IPs

Other qualifications include:

  • Strong verbal and written communication skills including interfacing with internal Customers, Sr. Management, and partners/OEMs such as HP, Dell, Lenovo, and Microsoft across cultures and geographic boundaries.

  • Experience driving multiple aspects of engineering, from intercept planning, architecture, design and development through feature execution, implementation, debug, production and launch.

  • Ability to simultaneously drive multiple internal IP customers and be able to work with key stakeholders to identify priorities, foresee technical issues, and implement lowest cost/risk solutions.

  • Must be capable of synthesizing complex information into clear messages, often speaking on behalf of SIIP Management.

  • The ability to alter messaging for various audiences while maintaining consistency across all communication channels is critical.

  • Must have strong leadership skills as demonstrated through work, school, or extracurricular work, including communication, stakeholder management, ability to delegate and lead others, and ability to work in an environment with change and ambiguity.

Other preferred qualifications:

  • Ability to drive cross organization initiatives or technical task forces to completion when required.

  • Detail oriented with an inclination to identify and improve processes.

  • Experience in communicating with and influencing a variety of stakeholders, including customers, and senior management plus the ability to multitask and work in a diverse and dynamic environment.

  • Proficient at managing multiple programs simultaneously and complete commitments on time.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Position of Trust. This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Talent Consultant.