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Intel SoC Design Engineer in Santa Clara, California

Job Description

A SoC Design Engineer oversees definition, design, verification, and documentation for SoC (System on a Chip) development, determines architecture design, logic design, and system simulations, defines module interfaces/formats for simulation; also, performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.

In addition to this, contributes to the development of multidimensional designs involving the layout of complex integrated circuits, performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing, analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Responsibilities include, but are not limited to:

  • Interface heavily with ASIC/SOC design teams to understand the design requirements

  • Resolve flows and methodology issues related to fullchip floorplanning, fullchip integration, Hard-IP integration, layout verification, and tapeout. Help foundry customers take their next-generation SOCs to tapeout by sharing design methodology knowledge and experiences obtained through internal design execution.

  • Take Intel's full-chip integration requirements into customer's full-chip designs.

  • Review customer's floor-plan for several key features at various milestones.

  • Define the full-chip verification tape-out sign-off requirements.

  • Lead the development of layout verification methodology and runset usage requirements and guidelines on Intel's latest process node.

  • Address issues from foundry customers by collaborating with various internal support teams.

  • Lead the development of the Hard-IP integration methodology concurrently with the IP development on the latest process node.

  • Work with Hard-IP team to define the boundary conditions and specs while improving overall ease of integration and usability.

  • Evaluate the next generation process technology challenges, primarily in physical-design and verification space, such as new DRC, density rules. Identify required future capabilities and new methodology definition for layout integration ahead of design start.


Minimum Qualifications:

  • Bachelor or Master of Science degree in Electrical Engineering, Computer Engineering or closely related field.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

Other Locations

US, Arizona, Phoenix

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....