Intel SoC Floorplanning and Structural Design Engineer in Santa Clara, California
The Scalable Data-Center Silicon Group (SDSG is searching for an energetic and passionate hands on physical design team member to handle physical design tasks from synthesis to closing blocks and the chip for tapeout.
We are looking for someone who has passion around improving the way we solve complex problems through the work of the team as well as their own direct contributions. Working experiences include digging in deep on technical challenges, empowering a team to succeed, and fostering technical guidance to development of junior employees.
Fullchip and block floorplanning, physical design, physical verification of SOC.
Responsibilities could include test chip development as well as product based SOCs.
Determines block and potentially full chip floorplan, working with packaging, design, and board level teams.
Responsible for block and/or top level clocking, power grid routing, bump & pin placement, memory placement in blocks. Floorplan the SOC, allocating area to blocks as required and negotiate with block owners as to area increases.
Own or work with full chip and block static timing engineers to close timing with required layout & timing ECO changes.
Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
Performs all aspects of the SoC physical design flow: synthesis, full chip and block floorplanning, place and route, timing and power to create a design database that is ready for manufacturing.
The ideal candidate will be able to demonstrate the following behaviors:
Ability to work effectively with both internal and external teams/customers is expected.
Ability to mentor other engineers and technically guide them.
Experience with silicon which include processor cores and custom logic working together.
Strong problem solving skills
Strong written and verbal communication skills
Capable of working in a high performing team to deliver the results required from the organization.
Facilitator of direct and open communication, diversity of opinion, and debate.
- Minimum Requirements:
BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 8+ years of relevant experience in SOC/system design/verification or MS degree with 6+ years or PHD with 4+ years of directly related experience with SOC Physical design.
Candidates must have the following:
Proven expertise in Silicon based product development.
Experience with designing/dealing with various type of external interfaces, like DDR, PCIe or similar.
The ability work as an individual and as part of a team to deliver a product starting from the creation of the spec, design, verification, and finally to tapeout.
Expertise in dealing and designing with complex IP's from different sources onto the same piece of silicon.
Understand system and package implications of the silicon design decisions.
Experience with ASIC based designs
Experience implementing new flows based on industry standard tools
Experience with implementing and working with multiple fabs and technology nodes
Inside this Business Group
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....