Intel Sr. Physical Design Engineer in Santa Clara, California
We are seeking an experienced structural physical design Synth/APR engineer to work with a dynamic team designing Intel's next generation IP for High Performance Computing and Artificial Intelligence products.
Responsibilities include but are not limited to:
Chip level floor-planning
RTL synthesis and APR using industry standard tools
Driving power, timing, and layout convergence of multiple designs
Debugging post-silicon circuit issues
BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 6+ years of industry experience in SOC/IP physical design including:
Demonstrable experience in RLS
Demonstrable experience in floor planning and routing
Demonstrable experience in physical design convergence and tape-in
Circuit design and feasibility
Interconnect design and analysis
Computer micro-architecture - translation of architectural specification into physical domain
Layout design understanding
RTL/Logic design (Verilog, VCS, etc.)
Strong written and verbal communication skills
Strong analytical ability and problem solving skills
Proficient in Synthesis tools like Design Compiler, APR tools like ICC/Astro, Static timing tools like PrimeTime, in scripting PERL and/or TCL
Please be informed that Intel is proactively trying to find candidates for Designers and that this position may not be available at this time
Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
US, Massachusetts, Hudson;
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